To obtain perfect interlacing of lines in alternate field scans of the video signal generated by a CCD imager, and at the same time to avoid attendant flicker, it is preferable to clock the image register with a clocking signal having an even number of clock phases. Two-phase clocking and variants thereof (uni-phase clocking, etc.) have not been completely satisfactory, because in order to establish direction of charge transfer it is necessary to differentially dope the semiconductive material in which the CCD charge transfer channels repose. Furthermore, a short-through between gate electrodes consecutive in the same polysilicon level, which could be tolerated in a multi-phase CCD, renders a two-phase CCD useless. Four-phase clocking requires a substantially more complex clocking generator than clocking with fewer phases. This increased complexity of clocking generation is required, not only for the image (or A) register of the field-transfer CCD imager, but also for its field storage (or B) register which is synchronously clocked with the A register during field transfer and for its output line (or C) register(s). Clock generation is even more complex when six-phase clocking is considered. Increasing the number of clocking phases for the A, B and C registers undesirably complicates the bussing of the clocking signals in the CCD imager, as well.
For these reasons CCD imagers of field transfer type are commonly operated with three-phase clocking, and perfect interlacing of lines in alternate field scans is approximated with varying degrees of success by one of several known methods. "Two-thirds interlacing" may be used, for example; or there can be control of image register clocking voltage amplitudes as described by D. F. Battson in U.S. Pat. No. 4,507,684 issued Mar. 26, 1985, entitled REDUCING GRAIN IN MULTI-PHASE-CLOCKED CCD IMAGERS and assigned to RCA Corporation. A fairly standard CCD imager fabrication technology for visible light CCD imagers has evolved at RCA Corporation. It uses three levels of polysilicon in which to form the gate electrodes receptive of the three clock phasings of the A, B and C registers. Charge transfer channels are buried, and the CCD imager is thinned to facilitate back-side illumination. Integrated-circuit clock generation circuitry for such CCD imagers has been developed and finds fairly standard usage with CCD imagers manufactured by RCA Corporation.
The compromise of three-phase clocking has been acceptable so long as CCD imager size has been relatively small (eight millimeter image diagonal or less), as has been the case for surveillance and portable broadcast cameras. But in the design of broadcast television studio cameras, the desire for increased resolution without sacrifice in imager sensitivity dictates a larger image size. Furthermore, there is a desire to use camera optics already commercially available for use with vidicons. These optics are designed for an eleven millimeter image diagonal. Battson in U.S. Pat. No. 4,507,684 has linked the problem of "grain" to partitioning noise associated with the gate electrode (or succession of gate electrodes) biased to establish a barrier between adjacent imager picture elements (pixels). Grain is acceptable as a practical rule-of-thumb so long as barrier length does not exceed five to seven microns. As image-register pixel size increases beyond twenty microns or so, using gate electrodes of substantially equal length in the direction of charge transfer three-phase clocking for all phases of clocking will result in the charge packets representative of image samples being excessively contaminated with partitioning noise. Images reconstructed from video signal response to these charge packets will be excessively grainy.
Accordingly, there has been a reconsideration by the inventor of the use of a greater number of clock phases in the image register of the CCD imager. This reconsideration has been made mindful of the fact that is undesirable from an economic viewpoint to have to develop a new silicon fabrication technology or to have to design completely new integrated clock generation circuitry.